1. Technical Field
The present invention generally relates to a semiconductor device and a layout structure thereof and, more particularly to a non-volatile memory cell and a layout structure of non-volatile memory device.
2. Description of the Related Art
Non-volatile memory (NVM) devices have the advantage of stored data would not disappear even when power supplied thereto is interrupted, and therefore have become one of widespread memory devices for data storage.
According to read-write cycle limits of memory devices, the non-volatile memory devices are classified into one type of multi-time programmable (MTP) memory device having repeatable read/write functionality and another type of one-time programmable (OTP) memory device only can be written a single time with data. In another aspect, from the viewpoint of device structure, the non-volatile memory devices primarily can be classified into double-poly non-volatile memory devices and single-poly non-volatile memory devices.
Since the non-volatile memory devices are compatible with the common complementary metal oxide semiconductor (CMOS) process, and thus are usually used in embedded memory fields. However, in an advanced logic process, the manufacturing process of the embedded memory devices by using the double-poly non-volatile memory devices is more complicated and has high cost, the device yield is also not good. Accordingly, in the advanced logic process, the single-poly non-volatile memory devices relatively have certain advantages and thus are regarded as more competitive memory devices in next generation.
FIG. 1 is a schematic, partial top view of a layout structure of single-poly multi-time programmable non-volatile memory device.
As illustrated in FIG. 1, a semiconductor substrate 100 has P-type well regions 112 and N-type Well regions 114 disposed therein. Moreover, a plurality of isolation structures 160 are disposed between the P-type well regions 112 and N-type Well regions 114. The conventional single-poly multi-time programmable non-volatile memory device includes a plurality of memory cells 110. Each of the memory cells 110 is consisted of a transistor 120 disposed in the P-type well region 112 and a capacitor 140 disposed in the N-type well region 114. The transistor 120 employs a poly-silicon layer g1 as a gate electrode, and uses two ion doped regions disposed in the P-type well region 112 and at two sides of the poly-silicon layer g1 respectively as a source electrode S and a drain electrode D. The capacitor 140 employs an ion doped region in the N-type well region 114 as a control gate CG of the memory cell 110, and uses a poly-silicon layer g2 over the N-type well region 114 as an electrode of the capacitor 140. The gate electrode of the transistor 120 and the electrode of the capacitor 140 are electrically connected with each other and constitute a floating gate FG. The floating gate FG is perpendicularly disposed over the P-type well region 112 and the N-type well region 114, and extends over a part of the isolation structures 160.
The memory cells 110 of the conventional non-volatile memory device are arranged in an array. The transistors 120 sequentially arranged along X-axis coordinate direction and the adjacent capacitors 140 sequentially arranged along X-axis coordinate direction are used as a repeating unit. Furthermore, a plurality of word lines WL extend along X axis coordinate direction and arranged in parallel in Y-axis coordinate direction, and the word lines WL are electrically coupled to the respective control gates CG of the capacitors 140 arranged along X-axis coordinate direction. A plurality of bit lines BL (not shown) extend along Y-axis coordinate direction and arranged in parallel in X-axis coordinate direction and perpendicularly crossing with the word lines WL, and the bit lines BL are electrically coupled to the respective drain electrodes of the transistors 120 arranged along Y-axis coordinate direction.
Still referring to FIG. 1, the conventional layout structure of non-volatile memory device takes one capacitor 140 and two transistors 120 as a minimum memory cell, and the layout design is that using one word line WL to control two bit lines BL.
However, the current development trend of memory device is toward higher memory density and the programming speed of memory device also is expected to be gradually improved. Therefore, how to achieve the above-mentioned aims will be one of important issues for the development of memory device.